1. Field of the Invention
The invention relates generally to charge coupled device image sensors and specifically to methods of improving sensor performance by smear signal and dark current signal reduction.
2. Description of Related Art
Charge couple devices (hereinafter CCDs) are widely used in video imaging and recording applications. The architecture of CCD video sensors generally follow the form dictated by the National Television Standards Committee (NTSC) for video broadcast standards. CCD video sensor designs need at least 488 TV lines vertically, 500 to 800 pixels per TV line, have an optical format of 4/3 aspect ratio, and generated field interlaced video at a frame rate of 30 Hz. CCD architectures which achieved the goals of the video format imaging requirements generally fell into two categories: Interline Transfer (ILT) or Frame Transfer (FT) image sensors. Other types of video sensors have also been developed such as full frame (FF), MOS X-Y, and charge injection devices (CID). This invention relates mainly to the ILT and FT image sensors and has little or no relevance to the other forms of video format image sensors.
Frame transfer sensors rely on the integration of an odd or even field of data, the quick transfer of that image field data to an optically opaque analog storage array, and the subsequent parallel to serial transfer of the video data to a camera circuit. An optically opaque storage array is a storage array that is covered by an optically opaque material such as an aluminum film so that the storage array is not photo-sensitive. The rapid vertical transfer of the image data from integration of the first video field is vital since the optical input onto the imaging section of the CCD sensor is continuous (not strobed or modulated during transfer). However, since vertical transfer requires a finite time to complete, there is always some fraction of image signal from subsequent integration fields collected in the vertical shift register during the field transfer to the storage region. The quantity of signal charge present in the video field which results from integration during the transfer time is said to be a smear signal offset to the proper video signal. Each pixel collects a fraction of the image charge as it rapidly passes through the image while transferring to the storage area. The quantity of smear is measured as a fraction of the nominal signal level and is proportional to the transfer time and the local optical power density. The visual effect of the smear charge, as it appears on a video monitor, is a vertical strip of excess brightness emanating from the bright source in the image. The stripe may be faint or saturated depending on the brightness of the source.
Interline transfer CCD image sensors solved the problem of transferring a field of image data during the integration of the next field of data by using an opaque vertical shift register (i.e., a shift register covered by an opaque material). The opaque vertical shift resigster is disposed adjacent to the photosensitive pixel. Signals from one field of pixels is very rapidly transferred to the vertical register and then transferred in a parallel/serial manner at the normal (60 Hz) field rate. The majority of the smear content is thus eliminated since the image data from the preceding field is shielded by the opaque film disposed over the vertical shift register from further integration during the readout even though the entire array is illuminated with the optical signal from the image plane. The penalty for this improved smear function is the reduction in optical aperture of the individual imaging pixel (by approximately 50%). Thus, the sensitivity of the sensor is diminished by 50%. Additionally, the ILT employs a relatively slow parallel to serial readout rate corresponding to 244 vertical lines read out in 1/60 sec. Even though the vertical readout registers are most likely shielded from a direct optical signal, the small amount of optical signal which "leaks" (e.g., via a phenomenon known as light piping) into the vertical register during vertical field transfer has substantial integration time to build up unwanted smear signal.
CCD image sensor pixel structures and processes have been continuously improved such that commercially available CCD image sensors used in both consumer camcorders and broadcast video systems have reduced smear content to -90 dB below the nominal signal level. Improved smear performance is realized by several techniques described herein and are used in the current embodiment of the invention. The present invention further improves on the prior art by applying very fast frame transfer techniques and very fast smear signal reset structures to reduce the smear signal content by an additional -20 dB to -30 dB. This smear reduction is accomplished while maintaining optimum optical aperture, signal charge saturation, antiblooming protection, electronic shuttering, and transfer characteristics for the CCD video image sensor.
CCD imaging devices which are comprised of combinations of interline transfer and frame transfer technologies (called frame interline transfer or FIT) have been reported. Such devices have been developed for the proposed HDTV video applications which involve larger, higher resolution arrays, higher data rates, smaller pixel dimensions, and different video signal formats to those of the standard RS170 video format. The prior art applied to HDTV format image sensors does in fact reduce smear signal by quickly clearing the image charge from the vertical interline shift registers into the light shielded frame storage registers. The current invention describes a CCD video image sensor device architecture which demonstrates an improvement over the prior art (FIT) for smear signal reduction.
In addition to the smear signal performance of a CCD sensor, several other performance factors are of concern. CCD image sensors experience thermally generated leakage currents which integrates the potential wells of the CCD shift register. The leakage current results in a background signal level known in the industry as dark current and is usually specified as a current density in nanoamps per square centimeter. The dark current is generated by both surface state and bulk traps or defects in the crystal and typically generate signal carriers (electrons in most CCD's) with a rate which doubles for every 7 degrees C in temperature change. Thus, if the room temperature (25 C) operating condition for dark current density is 1 nA/cm.sup.2, then the dark current density at 53 C is 16 nA/cm2. The dark current density is a characteristic of the silicon process and the device structure and may be lowered by reduction of bulk and surface generation sites.
Dark current density which has been established by the CCD processing can be reduced during the CCD operation by employing a clocking scheme for the CCD electrodes known in the industry as multi-pinned phase (MPP) operation. With this method, surface state related dark current electrons are recombined with holes pulled to the surface from the p-type regions adjacent to the CCD channels. Employing the MPP method, as well as various processing techniques, dark current can be minimized to values as low as 0.01 nA/cm2 at 25 C. This value is still finite and non-zero and still is subject to the same doubling rate as the operating temperature of the device increases. As the dark current signal increases the dynamic range or contrast ratio of the CCD sensor is reduced, which reduces the overall system performance.
Another CCD device performance parameter is radiation tolerance. Ionizing radiation sources, such as those found in vacuum space, can create damage to a CCD image sensor over the lifetime of the sensor. Mechanisms for this damage include generation of fixed oxide charge in gates and other insulator regions of the CCD sensor, silicon crystal displacement damage, as well as other effects. Crystal damage and surface state density alterations generally result in increased dark current density and reduced charge transfer efficiency over time. Fixed oxide charge results in threshold shifts, educed amplifier performance, and reduced charge transfer efficiency.
A CCD image sensor designed for the purpose of real time video imaging is generally described as an interlace format interline transfer (ILT) or frame transfer (FT) area imaging device.
The standards for the operation of and physical format of the CCD sensor are described by NTSC standards commonly known as RS170 video broadcast standards. These standards include specifications for image aspect ratio (4:3), number of video lines per picture height, interlacing scheme, and frequencies of operation.
The actual theory, operation, and construction of the CCD image sensor technology is voluminously described in the literature. Salient features of the CCD image sensor technology, as it applies to the current invention will be detailed.
Referring to FIG. 1, a CCD image sensor architecture which conforms to the RS170 video format comprises an interline transfer imaging architecture 11, a horizontal readout register 12, and an output amplifier structure 13. An alternative CCD video image sensor architecture is a frame transfer structure (FIG. 2) comprising a frame transfer imaging section 21, a field storage section 22, a horizontal readout register 23, and an output amplifier structure 24.
In FIG. 1 the interline architecture (hereafter ILT architecture) includes an integration site or pixel 14, a pixel to vertical register transfer region 15, and a vertical transfer register 16. Visible radiation from the imaged scene is focused onto the imaging array 11, and falls on the pixel which is typically a form of silicon photodiode. The pixel may also be constructed of an MOS gated region using doped polysilicon material as a somewhat transparent electrode. The pixel aperture is usually defined by a patterned layer of aluminum. An aluminum layer covers the vertical shift register 16 and reflects the light incident at that location. Light falling on the open pixel is converted to electrons and holes in the silicon substrate. Electrons are collected in potential wells in the silicon substrate formed at the pixel. After the integration time interval the charge from alternate pixels is transferred laterally to a receiving potential well in the vertical shift register. Electrons or signal charge from alternate pixels is transferred in alternate image fields corresponding to the NTSC television monitor scan sequence called interlacing. This transfer is affected by the application of a voltage to the MOS electrodes of the vertical shift register.
Once the charge is transferred to the vertical shift registers, the register electrodes have applied voltages in a clocked sequence such that the signal charge is transferred vertically downward in a line by line fashion. The signal charge is transferred to a horizontal CCD shift register 12 at the bottom of the array. The signal charge is transferred laterally in a serial fashion using voltages applied to the register electrodes in a clocked sequence. The signal charge is then converted to a voltage through a capacitive sense node and then the voltage signal is coupled to the external circuitry through a simple analog amplifier circuit 13.
The parallel to serial transfer of a frame of image information is thus completed in an interlace field sequence with each field having one-half of the number of video lines. The time interval allowed for the sequence to be completed is set by the NTSC standards at 30 frames per second.
Referring to FIG. 2, the frame transfer CCD architecture (hereafter FT architecture) includes an imaging region 21, a field storage region 22, a horizontal readout register 23, and an output amplifier 24. In the FT architecture, the entire imaging region is photoactive and no overlaying aluminum or other light shielding area is defined in the pixel. There are rows of CCD channel regions 25 covered by polysilicon electrodes which are similar in function to the vertical shift register of the ILT device. Integration sites are formed by the application of a static voltages to alternate polysilicon electrodes. Light from the imaged scene is focused onto the imaging array, transmitted through the polysilicon electrodes to create electrons and holes in the silicon substrate, and signal charge is collected in the potential wells of the integration sites. After integration the vertical registers are clocked at high speed into receiving register elements in the field storage section 22. The imaging section is then reset to a static potential. Alternate electrodes from those activated in the first integration are activated in the second field creating integration sites which are displaced by one pixel dimension vertically.
While the second field integration is taking place, the signal charge from the previous field is being transferred in the parallel/serial fashion from the storage register to the horizontal shift register 23 and out through the analog amplifier 24.
Referring to FIGS. 3A and 3B, graphic representations of video imagery are shown. FIG. 3A represents a frame of video imagery 31 with 488 lines of vertical resolution 32 and the corresponding video wave form signal generated at the output of the horizontal shift register. The number of horizontal resolution elements 35 is not established by NTSC standards but is typically 550 to 768 pixels per line. The graphic depicts imagery from a uniformly dark background with a bright target in the scene which is approximately 10% of the picture height.
A video wave form 33 indicates the odd field voltage output wave form from the CCD image sensor. The video signal from the bright object, for example an object located at line N 38, is at a value near to the peak output signal possible from the sensor. The region of video depicted as a white band running vertically is generally described as smear signal and results in unwanted signal in lines above and below the bright object in the scene 34. The amount of smear signal, shown at 37 of video line N 1, is measured from the reference level 36 (i.e., the dark background of the image that would otherwise be the signal corresponding to the particular pixel). The smear signal is usually specified as a fractional percentage of the nominal signal in the region of the bright object. The fractional value of smear signal can be as high as 10% to as little as 0.001% depending on the design of the image sensor pixel and readout structures.
FIG. 3B depicts the same scene as shown in FIG. 3A with the image smear virtually eliminated. Video wave form 38 shows no measurable smear signal as is characteristic of the present invention.
Equally objectionable is a dark signal depicted in FIG. 4. Dark signal 42, adding to background signal 41, is generated by several sources including surface state generation sites the oxide/silicon interface and bulk silicon generation sites. The control of dark current generation largely depends on the details of the silicon processing used as well as the purity of the bulk silicon starting material. The dark current generally results in unwanted background signal charge in the absence of optical input which can be viewed as point sources or collections of point sources in the image. The dark signal may also be seen as a largely uniform voltage offset of the video in the dark with gradual variations across the CCD sensor.
The generation sites for dark current in CCD image sensors generally follow a statistical thermal generation characteristic which predicts a doubling of dark current generation for every 7 degrees centigrade increase in substrate temperature. Thus, CCD image sensors are susceptible to reduction in dynamic range performance and a degradation of the signal to noise ratio when the sensor is subjected to elevated temperatures.
Additionally, dark current generation site density can be increased when the sensor is subjected to ionizing radiation sources such as X-rays and energetic charged particles such as electrons or protons. In vacuum space applications, CCD image sensors can be subjected to ionizing radiation which increases the dark current generation site density gradually over the lifetime of the device.
In the space imaging applications, as well as for other applications, it is necessary to reduce the smear content and the dark current content of the image signal. The invention improves the CCD video imaging technology by reducing the smear content and the dark current content in the imagery using a technique of rapid elimination of the unwanted signal charge during the blank period between the odd and even field readout sequences.
The present invention, the fast frame interline transfer (FFIT) CCD device, demonstrates the capability of simultaneously reducing smear signal and accumulated dark signal, beyond the capabilities of the prior art, through practicing the methods of the invention.